Switched-capacitor circuits are known. Such circuits are the product of circuit design techniques commonly used to miniaturize (integrate) components. In portable (hand-held) radio communication applications, components such as filters, integrators, differential amplifiers, comparators, summers, etc., are often reduced to integrated circuit (IC) form. When a capacitor is switched, by the switches of a switched-capacitor circuit, between a signal source to be sampled and the load, at a rate many times that of the frequency of the sampled signal, the capacitor will simulate the circuit behavior of a resistor between the source and the load. By combining capacitor(s), switched-capacitor(s), and operational amplifier(s), complex functions such as filtering can be implemented efficiently in IC form.
To reduce the current drain (energy consumption) of a switched-capacitor circuit, it is known to activate (or power-up) the operational amplifier (op-amp) associated with the switched-capacitor circuit only when the circuit function is needed, in the normal mode, and to fully deactivate the op-amp (or power-down) when it is not in use, in the power down or idle mode. This powering-down provides maximized energy savings since the majority of current is drawn by the op-amp when activated.
Referring to FIG. 1, a switched-capacitor circuit, implemented as a first order low-pass filter 10, is shown, as an example, illustrating the settling time problem. Settling time is defined to be the time interval, following the initiation of a specified stimulus to a system, required for a specified variable to enter and remain within a specified narrow band centered on the final value of the variable. The switched-capacitor filter 10 comprises an operational amplifier 16, a pair of switched-capacitors 12 and 14 (that simulate resistors when switched rapidly), and a non-switched feedback capacitor 22.
An input signal, V.sub.in, is coupled to the inverting input of the operational amplifier (Op-amp) 16 by a quadruplet of switches 181-184, collectively referred to as switch or switches 18. Similarly, a quadruplet of switches 191-194, is collectively referred to as switch or switches 19.
As is readily understood in the art, there are at least two phases of switching signals, generated by a multi-phase clock generator circuit, associated with the switches 18 and 19. If only two phases are generated, they are commonly called an EVEN (E) phase and an ODD (O) phase. Typically, these E and O signals are of complementary phases and are generated from a bi-phase non-overlapping clock generator circuit. The switching signals are considered to be non-overlapping when the respective switches they control are never in the closed state simultaneously (E, O=11). That is, the highs or logical ones of the ODD phase clock signal occur within the lows or logical zeros of the EVEN phase clock signal, and the logical highs or ones of the EVEN phase clock signal occur within the logical lows or zeros of the ODD phase clock signal (E, O=01, 00, or 10). Hence, during the EVEN clock phase, all the switches marked "EVEN" are closed simultaneously, then opened followed by a closure of all the switches marked "ODD", during the ODD clock phase. It is thus assured that no two adjacent switches are turned on at the same time.
When the switches 18 are closed for the EVEN phase, the current provided by V.sub.IN charges the capacitor 12. The charge accumulated on the capacitor 12, during the EVEN switching phase, is re-distributed, or discharged, to the capacitors 14 and 22 when the switches 18 and 19 are closed for the ODD phase.
As in a conventional active RC low-pass filter, the positive, or non-inverting, input of the Op-amp 16 is connected to an analog ground potential V.sub.AG. The term "virtual ground" or analog ground (V.sub.AG) is used commonly in analog circuit design to refer to a voltage potential, usually at the middle of the positive and negative power supply potentials, where an analog signal is referenced as zero signal potential.
The Op-amp 16 provides an output signal V.sub.out, a portion of which is fed back to the negative input of the Op-amp 16 by the feedback capacitor 22 and the feedback switched-capacitor 14 (in conjunction with the switches 19). Thus, the switches 181-184 and the switched-capacitor 12 form a switched-capacitor input network 20. Similarly, the switches 191-194 and the switched-capacitor 14 form a switched-capacitor feedback network 30. Hence, each switched-capacitor network forms a switched-capacitor resistive element or an equivalent resistive element, each having input and output terminals. With four switches shown, as connected, in the commonly known parasitic-insensitive configuration, each of the networks 20 and 30 also forms a parasitic-insensitive switched-capacitor network or resistive element.
Switched-capacitor network 20 is inverting the charging process, because the same clock phase is controlling, on both sides of the switched-capacitor, either the switches (182 and 184) connected to the input terminal and V.sub.AG or the switches (181 and 183) connected to V.sub.AG and the output terminal. Conversely, switched-capacitor network 30 is non-inverting the charging process, because the same clock phase is controlling, on both sides of the switched-capacitor, either the switches (192 and 194) both connected to V.sub.AG or the switches (191 and 193) connected to the input and output terminals. Either the inverting or non-inverting charging configuration can be interchanged, and used suitably, anywhere in a switched-capacitor circuit.
A power down (PD) control signal 51 is coupled to a port of the op-amp 16 to selectively turn the op-amp 16 ON, for normal mode operation, and OFF (the output is tri-stated or open circuited), for power down mode operation.
During normal circuit operation (normal mode), the control signal 51 is at a low logic level, which turns the op-amp 16 ON to provide the output voltage V.sub.out. When the control signal PD 51 is at a logic high level, representing a power down mode, the output node 28 of the op-amp is floating and essentially disabled with no power flow through the op-amp 16.
In other words, when the op-amp output is tri-stated, the powered-down configuration of the switched-capacitor circuit would be the same as if the op-amp were simply removed. If the E, O non-overlapping clocks remain switching, the circuit becomes a passive network whose node voltages are topologically dependent. Specifically, the continued switching of the switching capacitors 12 and 14 may convert the charges stored in all the capacitors 12, 14, and 22, into undesirable potentials. These stored voltage potentials may result in an undesired average output voltage V.sub.out.
If the E, O switches 18 and 19 are simply stopped at any of the non-overlapping states (E, O=01 or 10) or the open state (E, O=00), the node voltages will still float to undefined states, due to the presence of leakage currents. When the switched-capacitor circuit 10 is again powered-up by PD=0, node voltages will usually be in these non-V.sub.AG DC states which will only decay to V.sub.AG after circuit-dependent time constants.
For filters with low corner frequencies, these time constants may be as long as several milliseconds. The problem may be compounded if the offset of the input is varying due to preceding circuits also settling. Consequently, there is a significant delay before a powered-up path settles.
In communication applications, such as in a radio, the switched-capacitor filter 10 is implemented as an integrated circuit (IC) for audio filtering of communication signals. Hence, if a speaker type output load is coupled to the output node 28, during a transition to the power up mode, i.e., the PD 51 signal goes from high to low, a large transient output voltage spike may occur. This large transient may be audible and objectionably loud.